Custom Paralleled VBSME Datapath on Xilinx Artix-7 FPGA
Custom Assembly, Verilog, Vivado
December, 2023
Overview:
Designed a highly optimized Variable Block Size Motion Estimation datapath for a university competition.
Technical Aspects:
- Developed a parallel-pipelined architecture with custom assembly language.
- Achieved low path delay (9.067ns) and execution time (1356ns) on FPGA.
- Utilized Verilog and Vivado for hardware implementation and testing.
Impact & Insights:
Demonstrated excellence in hardware optimization but missed recognition due to minor display error.
Skills Developed:
- FPGA design and testing
- Hardware optimization techniques
- Team collaboration on competitive projects
Lessons Learned:
Reinforced the importance of attention to detail in high-stakes projects.