Pipelined Datapath on Xilinx Artix-7 FPGA

MIPS Assembly, Verilog, Vivado

December, 2023

evanwmart/uni-ECE369A-lab

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Overview:

Created a pipelined MIPS datapath with forwarding and hazard detection for execution on FPGA.

Technical Aspects:

• Designed and implemented a programmable MIPS datapath in Verilog.
• Simulated and tested on Xilinx Artix-7 FPGA using Vivado.
• Integrated forwarding logic to optimize performance.

Impact & Insights:

Demonstrated proficiency in pipelining techniques for efficient hardware systems.

Skills Developed:

• Verilog programming
• Pipelining and hazard detection
• FPGA simulation and testing

Lessons Learned:

Gained practical experience in hardware design and optimization.